IBM Unveils Revolutionary Sub-1-Nanometer NanoStack Chip Technology for AI Applications
IBM has introduced groundbreaking sub-1-nanometer chip technology based on a new 3D NanoStack transistor architecture at the 0.7 nm node. This technology aims to pack nearly 100 billion transistors on a small die, doubling the density of previous chips. The new chips offer higher performance, lower energy consumption, and reduced costs per unit of compute power, making them ideal for AI applications.
The NanoStack design features a three-dimensional, nanosheet-based transistor structure that stacks and staggers CMOS devices vertically. By bonding two nanosheet transistors into a single vertical structure, each tier can be optimized independently, allowing for different channel materials, dielectrics, and metals to be used. This design can be extended through multiple generations, potentially reaching down to 1 angstrom in the future.
IBM's 0.7 nm technology promises up to 50% higher performance at the same power or up to 70% lower power for the same performance compared to its 2 nm node. The company also achieved a 40% improvement in the scaling of static random-access memory (SRAM) cell area, which could benefit AI accelerators reliant on on-chip memory bandwidth. The technology has been experimentally validated in the lab, demonstrating real computation capabilities.
IBM's NanoStack technology represents a significant advancement in chip design, moving towards three-dimensional scaling and offering performance gains crucial for AI applications. While the technology is still in the research phase, IBM envisions it being used in various computing devices, including CPUs, GPUs, mobile SoCs, and SRAM arrays. The company aims to replace its nanosheet-based architecture with NanoStack as the mainstream leading-edge design at the sub-1 nm node.